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Role Purpose :
The Physical IP Division inside ARM creates Physical IPs of various types like Standard Cells, Memory, and Interface which are extensively used by thousands of IC designers around the world to design leading edge chips. We are currently marketing and developing solutions from 180nm to 10nm and research work on 7nm solutions is happening at various ARM design centres worldwide.
A dedicated team of experienced professionals in software, methodology and flow development aids this process of creating Physical IPs for leading edge chips. Forming part of the ARM Physical IP Division, the Modelling and Methodologies Group develops Front end models for Standard Cells, Memory and Interface physical IP as well as creates methodologies to validate the physical IP. The front end model development involves creation of Simulation, ATPG, Low Power views which gets used during SoC IP validation. The group also focuses on developing methodologies like Correlation, Simulation, Synthesis, DFT, ATPG, Logic Equivalence, Place and Route etc. that makes the IP robust and high quality while reducing the cost with improved efficiency.
Role & Responsibilities :
The candidate’s responsibility includes development, validation and maintenance of the Verilog simulation models for physical IP. Along with that candidate would have complete ownership of the DFT and ATPG models that are used in SoC flow. The role offers a potent opportunity to interact with accomplished circuit designers worldwide for design of best in class Physical IPs on the latest technologies nodes like 16nm, 10nm, 7nm etc. Candidate would serve as interface between the engineering teams, external customers and the third party EDA vendors to track resolution of issues associated with front end validation tools like Functional simulators, LEC, ATPG, STA etc.
The candidate would be involved in defining/updating the methodology for validation of Physical IPs, understanding the requirements of circuit designers spanning across multiple ARM sites worldwide. He is expected to work closely with software team for the implementation and validation of the flows in order to create most efficient and high quality solutions for the users. The candidate would be provided opportunity to develop his skill sets to develop his expertise in front end or back end flows. He is expected to be proactive in supporting the flows developed by the design automation team.
Qualification & Experience :
+ Bachelors or Master’s Degree in Electronics Engineering or equivalent
+ 0-1 years of engineering experience in Verilog modelling and verification
Characteristics & Requirements :
+ Quick learner, good problem solving and debugging skills
+ Willingness to be flexible and accept new challenges
+ Capable of working as a team player or independently
+ Good analytical and reasoning skills
+ Enthusiastic and self-motivated
+ Good communication skills
Essential Technical Experience :
+ Good understanding of digital circuits fundamentals and SoC concepts
+ Working knowledge of scripting tools (TCL, Perl)
Desirable Technical Experience :
+ Experience with Verilog modelling and verification
+ Experience with Frontend flows like Simulation, Synthesis, ATPG and Logic Equivalence
About Company : Arm technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. Our advanced, energy-efficient processor designs are enabling the intelligence in 100 billion silicon chips and securely powering products from the sensor to the smartphone to the supercomputer. With more than 1,000 technology partners including the world’s largest business and consumer brands, we are driving ARM innovation into all areas compute is happening inside the chip, the network and the cloud.All Arm trademarks featured on this company page are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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