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Learnyzen Hiring Fresher Interns (VLSI) At Bhuaneshwar

Posted On 30-08-2016 At 09:15 AM

REF ID : 8593

Designation/Level : ASIC Intern 

Eligibility : ME/M.Tech(CSE, EEE, Electrical, ECE, VLSI Design, Instrumentation & EIectronics), MSc(CS, Electronics),BE/B.Tech(Electronics, EEE, ECE, Electronics & Instrumentation)

Year Of Passing : 2015/2016 and before

Experience Required: Freshers

Type : Internship / Projects

Duration: 6 months

Location: Bhubaneswar

Internship highlights: 

Digital Design & Verification  – Linux Shell Scripting/Python  – Digital fundamentals – ASIC design and verification flow – Verilog language – Verilog for design and verification

Advance Digital  Design/Verification – System Verilog Language – UVM Methodology – Verification Project Flow – AMBA protocols (APB/AXI)


500+ hours of rigorous engineering

Guidance by actual VLSI engineers

Batch size is limited to 5

Acquire skills equivalent to 1+yrs in industry

more info at :



Complete knowledge on Advance Verification Methodology (System Verilog, UVM etc)

Working knowledge on Advance Simulation Tools(Questa)

Opportunity to work on real industry projects

100% placement assistance

Certificate of  work experience  

Skill – Hands-on / Mandatory : Digital Electronics Fundamentals, C Programming

Skill – Knowledge/ Preferred : Verilog  

Office at: Suite # 226, 2nd Floor, OCAC Tower, Acharya Vihar(RRL-PO), Bhubaneswar


Mail your resume at:

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